The present invention relates to analog integrated circuits, especially integrated circuits implemented using insulated gate field effect transistors (IGFETs).
Integrated circuits (“chips”) which implement some types of mixed signal systems include a digital core having a CPU and/or a digital signal processor (DSP), various memory blocks, and analog interface circuitry. In such case, the analog interface circuitry typically includes input/output circuitry, a digital-to-analog converter and/or an analog-to-digital converter, and a radio frequency front end interface, among others. Other such chips have an analog core at their centers, the analog core including a receiver complex and/or a transmitter complex, which is surrounded by digital logic for a variety of functions. In such chips, both the digital and analog circuitry are constructed from insulated gate field effect transistors (IGFETs) fabricated in a technology, e.g., referred to as “complementary metal oxide semiconductor” (CMOS) technology. Because CMOS was traditionally designed to support digital circuitry, the analog circuits of such mixed signal chips are forced to cope with the constraints of digital circuitry which dictate the evolution of CMOS technology. For example, one constraint of digital circuit design is the scaling of the power supply voltage with increasing circuit density and speed. Unfortunately, in analog circuits, harmonic distortion introduced by transistors increases drastically with a reduction in the power supply voltage. On the other hand, alternating current (AC) parameters such as junction capacitances and gain-bandwidth products improve with technology evolution, allowing better RF performance.
For a given power budget, it has been found that the performance of analog circuitry decreases when advancing from one generation of technology to the next, due to the reduction in the power supply voltage. Often, this occurs because the threshold voltages of the transistors cannot be scaled in proportion with the scaling of the power supply voltage. To maintain the anticipated performance, one must achieve the same difference in peak voltage above the threshold voltage as in the prior technology generation. However, such can only be achieved by not scaling the power supply voltage to the same degree as for the digital circuitry of the chip, or by reducing the threshold voltage. Either such way causes the power consumption to increase. In fact, an increase in the performance of analog circuits generally comes at a cost of higher power consumption.
Another concern of mixed signal chips is gate leakage current. Gate leakage current mainly depends on the voltage bias between the gate and source, referred to as “gate to source bias,” and the size of the gate. Undesirable results of gate leakage currents include the need to account for an input bias current at the gate of the transistor, gate leakage mismatch and shot noise. Here, an input bias current caused by gate leakage in an MOS transistor is similar to the base current of a bipolar transistor, except that the conductivity of the transistor depends upon the width to length ratio of the MOS transistor, as well. The input impedance of a MOS device consists of the conventional input capacitance and a parallel tunnel resistance due to gate leakage. In a 90 nm MOS technology, for signal frequencies higher than 1 MHz, the input impedance is predominantly capacitive and the MOS transistor behaves as a conventional MOS. For this reason, MOS transistors having thin oxide capacitances are not suitable for certain low-frequency applications like PLL filters and hold circuits. However, for signal frequencies above 1 MHz, the input impedance becomes predominantly resistive and the gate leakage dominates. At such higher frequencies, gate leakage mismatch exceeds conventional threshold voltage mismatch tolerances.
Matching generally limits the achievable level of performance on analog circuits. One way to reduce threshold voltage-related mismatch is to increase the area of the MOS transistors. However, gate leakage takes on the appearance of an extra spread source. This, in turn, places an upper bound on the amount of increased area that can be used to decrease the threshold mismatch. It is found that, with increased transistor area, the conventional threshold spreading contribution decreases. However, at the same time, the gate leakage spread contribution increases. Thus, the maximum usable transistor area is limited by the spreading of the gate leakage.
The problem only becomes more significant for the 90 nm and 65 nm generations, wherein the maximum area is about 104 μm2 and 103 μm2, respectively. To reduce gate leakage, one strategy is to provide a higher supply voltage on critical parts of the circuitry, so that these circuits can be constructed using transistors which have thicker gate oxides. The lifetime of an MOS transistor is dominated by the magnitude of the electric field in vertical and lateral directions, and the electric field across the junctions. Three life-time-determining mechanisms regarding to these fields are denoted as oxide breakdown, hot-carrier degradation and junction breakdown, respectively.
Relaxing design ground rules to trade performance for higher yield and reliability is one way of responding to the aforementioned challenges. However, other ways of responding are to use circuit solutions to deal with problems such as avoiding gate oxide breakdown due to high gate to substrate stress, as well as the shifting of the MOS threshold voltage level due to high electrical field induced hot carrier injection, etc. Cascade circuits are one known way of protecting devices from high voltage stress in circuits having outputs that swing from rail to rail. However, cascade circuits are unsuitable for use in many types of analog circuits, because signals in analog circuits do not swing from rail to rail. More new techniques are described in the following sections.
U.S. Pat. No. 6,377,075 to Wong describes one way for addressing hot carrier degradation and gate oxide breakdown in a digital signal circuit as opposed to an analog signal circuit. FIG. 10 thereof shows a ten-transistor inverter. The inverter circuit addresses high gate stress applied by 10 V power supply Vdd to the input devices M1, and M4 by adding two extra devices M6, M5 and two extra power supplies denoted therein as “pgate” and “ngate”. Two more devices M2 and M3 are added for reducing the stress applied to the input devices M1 and M4 due to hot carrier injection. Still other devices M8, M9 and M7 and M10 are added to decrease the amount of gate leakage currents below the threshold voltage (“sub-threshold leakage”) of transistors M1 and M4. While addressing the problems of gate stress and hot carrier injection, the circuit described in this patent comes at a cost of increased circuit size, complexity and power consumption.
U.S. Pat. No. 5,726,589 to Cahill et al. describes another way of addressing hot carrier related degradation. FIG. 11 of that patent illustrates an NFET device 12 which is protected from hot-carrier degradation by circuitry which delays the transistor from turning on until the drain to source voltage of the transistor has dropped below the voltage at which hot carrier injection is most prevalent. Such delayed turn-on time could lead to the transistor having decreased speed. Accordingly, a better way is needed to protect against hot carrier degradation and also maximize transistor speed.
U.S. Pat. No. 5,369,312 to Oh et al. describes another way of addressing hot carrier degradation. FIG. 12 of that patent shows a circuit in which two transistors Q1 and Q2 are stacked in cascade, and a third transistor Q3 operates to bias an intermediate node voltage at roughly half of the level of the supply voltage. Stacking devices in cascade configuration tends to work well only when the level of the supply voltage is sufficiently higher than the sum of the threshold levels of the stacked devices. Typically, the threshold voltages are 0.6 V or more. Thus, when the power supply voltage level is lower than some level, e.g., about 2.0 V, the reduced “headroom” afforded to differential amplifier type analog circuits can cause them to malfunction. As the power supply voltage is constrained to low levels and further scaled with the introduction of newer technologies, there comes a point when the stacking of transistors in cascade cannot be used with transistors having typical threshold voltages.
The problems of the prior art are apparent from a study of particular types of circuitry. FIG. 1 illustrates a current mirror circuit 10 according to the prior art. The current mirror circuit 10 outputs reference currents I1, I2, I3 which are generated as “mirror” currents in fixed proportion to a source current I0. When the threshold voltage and the size of each PFET Pi (i=1 to n) equals the threshold voltage and the size of PFET P0, then the reference currents I1, I2, I3, . . . In all have the same magnitude and sign as I0.
The current mirror circuit 10 is turned on and turned off by a power down control signal PDWN. The current mirror circuit is powered on when PDWN is held at ground. Under such condition, all of the pull down n-type FETs (“NFETs”) Ni (i=1 to n) are turned off and the pull up p-type FET (“PFET”) Px is turned off. However, when the current mirror circuit 10 remains in the powered down condition for a long time, or is frequently switched between the powered on and the powered down condition, hot carrier degradation and/or gate to substrate bias eventually cause the threshold voltages of the PFETs P1 to Pn to shift to a different level than that of P0. This occurs because of the different conditions under which PFET P0 is biased than the PFETs P1 to Pn in the powered off condition. When the current mirror circuit 10 is powered down, the gate to drain bias voltage of the PFETs P1 to Pn is at the power supply voltage Vdd, while the gate to drain bias voltage of PFET P0 is at zero volts due to the conductor which ties the gate of P0 to its drain. If such condition is maintained for a sufficiently long time, the threshold voltage (Vt) of the PFETs P1 through Pn shift to a different level than the threshold voltage of PFET P0, causing the magnitude of the reference currents I1, I2, etc. output by the PFETs P1 to Pn to change to a value different than the reference current I0 output by PFET P0.
In another example illustrated in FIG. 2, a reference voltage generator circuit 20 is arranged to apply little stress in the form of a drain to source bias voltage to an n-type FET N2 (“NFET”) which has a thin gate oxide. The circuit 20 generates a reference voltage level (Vdd−i22×R1) by a voltage drop of a current i22 across the resistor R1 from a power supply Vdd. Here, current “i” is mirrored from a reference current i24 conducted by a first NFET N1 having a gate terminal and a drain terminal which are both conductively connected to a gate terminal of a mirror NFET N2. In order to protect the mirror NFET N2 from experiencing high Vds stress, an additional resistor R2 is provided.
Since NFET N2 has a thin gate oxide, the drain to source voltage Vds needs to be maintained at a value of less than one volt. However, when the power supply voltage Vdd has a value such as 1.9 V, resistor R2 requires large size, which occupies a large area of an integrated circuit containing the voltage generator circuit 20. Also, the source NFET N1 and the mirror NFET N2 are stressed differently when the voltage generator circuit 20 is powered down. As in the above-described example, the gate of NFET N1 is tied to the drain of NFET N1, but this is not the case with NFET N2. For this reason, the resulting different gate to source bias voltages applied to NFET N1 and NFET N2 may cause the threshold voltage of NFET N2 to shift which can cause the transistors' threshold voltages to mismatch. Another problem of the voltage generator circuit 20 is that the PFET switch P1 adds inaccuracy to the reference voltage output level due to its contribution to resistance in the conductive path, adding an imprecise, variable amount of resistance to the circuit which is not easy to model. Accordingly, it would be desirable to eliminate PFET P1 from the circuit.
In another example illustrated in the prior art diagram of FIG. 3, a problem is highlighted of a conventional differential amplifier 30 such as an operational amplifier. To achieve high performance, low-Vt (low threshold voltage) and thin-oxide NFETs can be used for the pair of input devices T0 and T1. One reliability concern is that when the differential amplifier 30 is powered on the gate to substrate biases applied to NFETs T0 and T1 are too high, given that the substrate node of the NFETs is tied to ground. When the differential amplifier 30 is powered down, T0, T1 as well as the tail device T2 are subjected to high drain to source voltages (high Vds stress), since both input signals AN and AP, as well as the bias voltage at the gate of the tail device T2 are held at ground. These biasing conditions place voltage stresses on the transistors T0, T1 and T2 which can lead to insufficient reliability.
As mentioned above, in some analog circuits, good performance cannot be obtained when stacking FET devices in cascade which have typical threshold voltage levels such as 0.6 V. This is particularly true in circuits where the power supply voltage level is low in relation to the threshold voltage of the devices used therein. In some such circuits, attempts are made to improve the relationship by using low-Vt NFETs and PFETs in place of some of the cascaded FETs. One such example is shown in FIG. 4, in which a prior art hysteresis comparator 40 includes PFETs P6 and P7, which are stacked in cascade with NFETs N8 and N9, respectively. In such circuit, a first PFET P15 controls whether the comparator 40 is operated in AC or DC mode operation. The second PFET P6 is used to generate a current in fixed proportion to the current flowing through PFET P4, i.e., as a mirror current. In this circuit 40, NFETs N1 and N2 are low-Vt devices to which input signals INN and INP are applied, respectively. NFETs N8 and N9 function as tail devices for providing a current source to pull up or pull down the voltage at the output node indicated at “Out”. In this design, other than the PFET P15 and the NFETs N8 and N9, all of the transistors are low-Vt, thin-oxide devices.
With continued reference to FIG. 4, in order that current be accurately tracked from first stage transistors P4, N2 to the second stage at transistor P6 and from first stage transistors P3 and N1 to transistor P7, the transistors P6 and P7 are low-Vt devices. While such a design results in improved matching between the transistors, long-term reliability is not optimum in the circuit 40 because the low-Vt PFETs P6 and P7 are subjected to high drain to source bias (high Vds stress) due to the output node swinging from rail to rail. When the output is at ground, the low-Vt P6 device is stressed to the full amount of the power supply voltage Vtr. The high drain to source voltage stress makes hot carrier injection a concern for the low-Vt devices P6 and P7.
It bears noting that the long-term reliability problem cannot be solved simply by substituting such low-Vt PFETs P6 and P7 with high-Vt devices having a thicker oxide and longer channel length. Such substitution would drastically degrade the performance of the comparator because high-Vt devices used in the place of transistors P6 and P7 would not be capable of accurately mirroring the current from the corresponding low-Vt devices P3, P4 to which their gate terminals are tied. When there is a mismatch in the threshold voltages, the comparator circuit 40 fails at some worst process corners.